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[ak7719] ms1351-e-00-pb 2012/01 1 the ak7719 is a highly integrated digi tal signal processor (dsp) with f our digital interface ports. akm?s dsp core is optimized for both narrowband and wideband voice processing, as well as full bandwidth digital audio processing. an integrated clock generator for the dsp master clock eliminates the need for external clocks. the ram-based dsp can be progra mmed for user requirem ents. the ak7719 is housed in a 25-pin csp package. it is a very low pow er device, suitable for mobile applications. embedded dsp - flexible programming with built-in program and data memories - hardware accelerator - word length: 24-bits (data ram 24-bit floating point) - multiplier 20 x 20 ? 40-bits (double precision available) - divider 20 / 20 ? 20-bits - alu: 44-bit arithmetic operation (with 4-bit overflow margin) 24-bit floating point arithmetic and logic operation - program ram: 4096w x 36-bits - coefficient ram: 2048w x 20-bits - data ram: 2048w x 24-bits (24-bit floating point) - offset register: 32w x 15-bits - delay ram: 16384w x 24-bits(24-bit floating point) - 5625 steps at 16khz sampling rate, 1875 steps at 48khz sampling rate - internal clock generator audio interface format - 24-bit left justified, i 2 s, - 16/24bit linear, 8-bit a-law, 8-bit -law pcm - sampling rate 8khz ~ 48khz - up/down sampling rate converter for port#2 (8khz 16khz) c i/f: i 2 c-compatible, spi operational, sleep, power down power supply vdd (dsp core): 1.2v 0.1v tvdd (pcm i/f): 1.6v ~ 3.6v operating temperature range: -20 c ~ 85 c package: 25-pin wl-csp (2.62mm x2.93mm, 0.5mm pitch) power consumption: 6.2ma (7.5mw) typ. (narrowband hands free mode operation) general description features low power dsp for voice and audio processing ak7719
[ak7719] ms1351-e-00-pb 2012/01 2 block diagram memory din2 dout2 sdin2 sdout2 sync2 bclk2 din1 dout1 bclk1 sync1 sdin1 sdout1 vdd tvdd vss pdn dspclk akm dsp core control interface si/cad1 csn/scl so/sd a i2c sclk/cad0 sdin3 sdout3/gp0 pcm interface1 (port#1) dout3/gp0 din3 pcm interface3 (port#3) rdy wdt / crc sto/rdy sync3/jx1 bclk3/jx0 cgu (clk gen unit) jx1 jx0 test din4 dout4/gp1 sdin4 sdout4/gp1 pcm interface2 (port#2) pcm interface4 (port#4) figure 1. block diagram
[ak7719] ms1351-e-00-pb 2012/01 3 ordering guide AK7719ECB -20 +85 c 25-pin csp (0.5mm pitch) black type akd7719 evaluation board for ak7719 pin layout a b c e d 5 3 4 1 2 top view mark index edc a b 5 3 4 1 2 bottom view 5 pdn sdin1 sdout1 bclk1 sync1 4 vdd bclk3/ jx0 sdin3 sdout3/ gp0 sync2 3 vss sync3/ jx1 test sto/ rdy bclk2 2 tvdd i2c sdin4 sdou4/ gp1 sdin2 1 si/cad1 sclk/ cad0 csn/ scl so/ sda sdout2 a b c d e top view
[ak7719] ms1351-e-00-pb 2012/01 4 pin/function no pin name i/o function a4 vdd - core power supply pin 1.2v a2 tvdd - i/o power supply pin 1.6 3.6v a3 vss - ground pin 0v a5 pdn i p power-down mode pin ?h?: power-up, ?l?: power-down, reset the control register. the ak7719 must be reset once upon power-up. sto status output pin (active high) (strdy bit = ?0?) d3 rdy o data write ready output pin for control i/f (strdy bit = ?1?) e5 sync1 i frame sync 1 pin d5 bclk1 i serial data clock 1 pin ak7719 goes into standby state when bclk1 is not present. b5 sdin1 i serial data input 1 pin c5 sdout1 o serial data output 1 pin e4 sync2 o frame sync 1 pin e3 bclk2 o serial data clock 2 pin e2 sdin2 i serial data input 2 pin e1 sdout2 o serial data output 2 pin sync3 frame sync 3 pin (selpt bit = ?1?) b3 jx1 i conditional jump 1 pin (selpt bit = ?0?) bclk3 serial data clock 3 pin (selpt bit = ?1?) b4 jx0 i conditional jump 0 pin (selpt bit = ?0?) c4 sdin3 i serial data input 3 pin sdout3 serial data output 3 pi n (seldo3 bit = ?0?) d4 gp0 o dsp programmable output 0 pin (seldo3 bit = ?1?) c2 sdin4 i serial data input 4 pin sdout4 serial data output 4 pin (seldo4 bit = ?0?) d2 gp1 o dsp programmable output 1 pin (seldo4 bit = ?1?) b2 i2c i control interface mode select pin ?h?: i 2 c, ?l?: spi sclk serial clock input pin spi (i2c pin = ?l?) b1 cad0 i slave address 0 input pin i2c (i2c pin = ?h?) csn chip select pin spi (i2c pin = ?l?) c1 scl i control interface clock input pin i2c (i2c pin = ?h?) so o serial data output pin spi (i2c pin = ?l?) d1 sda i/o control interface i nput/output acknowledge pin i2c (i2c pin = ?h?) si serial data input pin spi (i2c pin = ?l?) a1 cad1 i slave address 1 input pin i2c(i2c pin = ?h?) c3 test i test pin (pull-down resistor) must be connected to vss. note 1. all input pins must not be allowed to float. note 2. i2c and cad0/1 pins must be fixed to ?l? (vss) or ?h? (tvdd).
[ak7719] ms1351-e-00-pb 2012/01 5 dsp block diagram cp0, cp1 dp0, dp1 data ram 2048w x 24-bit mpx20 mpx20 x y multiply 20 x 20 40-bit micon i/f control pram 4096w x 36-bit dec pc sta ck: 5 leve ls(m ax) mul dbus s hift a b alu 44-bit overflow margin: 4-bit dr0 3 over flow data generator division 20 20 20 peak detector serial i/f cbus(20-bit) dbus(24-bit) 40-bit 24-bit 40-bit 44-bit 40-bit 16384w x 24-bit ptmp(lifo) 6 x 24-bit dlp0, dlp1 din1 2 x 16/24-bit 2 x 16/24-bit 40-bit dout1 tmp 12 x 24-bit 2 x 16/24-bit dout2 dout3 2 x 16/24-bit 2 x 16/24-bit din3 din2 2 x 16/24-bit accelerator offset reg 32w x 15-bit 2 x 16/24-bit dout4 2 x 16/24-bit din4 delay ram coefficient ram 2048w x 20-bit pointer
[ak7719] ms1351-e-00-pb 2012/01 6 handling of unused pins unused i/o pins must be connected appropriately: pin name setting sto/rdy, sdout3/gpo, sdout4/gp1 leave open sync1, bclk1, sdin1, sdin2, sdin3, sdin4, sync3/jx1, bclk3/jx0, test connect to vss. pin states in power-down mode the table below shows pin stat es when the pdn pin= ?l?. no pin name i/o pin state sto d3 rdy o low c5 sdout1 o sdin2 data output e4 sync2 o sync1 data output e3 bclk2 o bclk1 data output e1 sdout2 o sdin1 data output sdout3 d4 gp0 o sdin4 data output sdout4 d2 gp1 o sdin3 data output so o low level (i2c pin = ?l?: spi) d1 sda i/o hi-z (i2c pin = ?h? :i 2 c) absolute maximum ratings (vss=0v; all voltages are with respect to ground.) parameter symbol min max unit power supply voltage (dsp core) vdd ? 0.3 1.6 v power supply voltage (digital i/o) tvdd ? 0.3 4.1 v input current (except for power supply pins) iin - 10 ma input voltage vind ? 0.3 tvdd+0.3 v operating ambient temperature ta ? 20 85 c storage temperature tstg ? 65 150 c warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operation condition (vss=0v; all voltages are with respect to ground.) parameter symbol min typ max unit supply voltage range (dsp core) vdd 1.1 1.2 1.3 v supply voltage range (i/os) tvdd 1.6 1.8 3.6 v note 3. the power-up sequence with vdd and tvdd is not cr itical. the pdn pin should be held ?l? when power is supplied. the pdn pin is allowed to be ?h? after all power supplies are applied and settled. note 4. the external pull-up resistors at the sda and scl pins should be connected to tvdd voltage or less. warning: akm assumes no responsibility for the usage beyond the conditions in the datasheet.
[ak7719] ms1351-e-00-pb 2012/01 7 electric characteristics (ta=-20oc~85oc; vdd=1.2v, tvdd =1.6v~3.6v; vss =0v) parameter symbol min typ max unit high level input voltage vih 70%tvdd v low level input voltage vil 30%tvdd v high level inptu voltage iout=-200 a ( note 5 ) voh tvdd-0.2 v low level input voltage iout= 200 a ( note 5 ) vol 0.2 v tvdd 2.0v 0.4 v sda low level output voltage iout=3ma tvdd < 2.0v vol 20%tvdd v input leak current iin 10 a note 5. except for the sda pin. (ta=25oc; vdd=1.2v; tvdd=1.8v; vss =0v, fin=1 khz, fs=8khz 16 bit (fs bits=0h, law bits = 0h, dif bit = 2h, dsp running with programmed connecting din1 with dout2 and din2 with dout1. parameter min typ max unit power supplies: power-up (pdn pin = ?h?) dsp-operational state all circuit power-up vdd - 1.7 - ma tvdd vdd=1.2v tvdd=1.8v ( note 6 ) - 0.02 - ma power consumption - 2.1 mw all circuit power-up vdd - 20 ma tvdd vdd=1.3v tvdd=3.6v ( note 6 ) - 2.0 ma power consumption - 33.2 mw power-down state (pdn pin = ?l?), ( note 7 ) vdd - 2.4 8 a tvdd - 0.2 1 a note 6. the current of vdd, tvdd ch anges depending on the system frequency and contents of the dsp program. note 7. all digital input pins are fixed to tvdd or vss. dc characteristics power consumption
[ak7719] ms1351-e-00-pb 2012/01 8 system clock (ta= -20oc ~ 85oc, vdd=1.2v, tvdd= 1.6v ~ 3.6v, v ss=0v) cl=20pf (except sda pin) or 400pf (sda pin); unless otherwise specified parameter symbol min typ max unit normal operation mode: sync1/3, bclk1/bclk3 input timing sync1/3 input timing sync1/3 frequency fs 8 48 khz bclk1 input timing ( note 8 , note 9 ) fbclk 64 3072 khz bclk1/3 pulse width low tbckl 0.4 x tbclk ns bclk1/3 pulse width high tbckh 0.4x tbclk ns note 8. sync1 and bclk1 or sync3 and bclk3 should be sy nchronized and their sampling rates (fs) should be stable note 9. required fbclk: 2 (data length set by law bit) x sync2 frequency reset and standby (ta= -20oc ~ 85oc, vdd=1.2v, tvdd= 1.6v ~ 3.6v, vss=0v) parameter symbol min typ max unit pdn ( note 10 ) tpdn 600 ns note 10. the ak7719 can be reset by bringing the pdn pin = ?l? upon power-up. serial data interface (ta= -20oc ~ 85oc, tvdd= 1.6v ~ 3.6v, vss=0v, cl=20pf) parameter symbols min typ max unit sdin1, sdin3, sdin4, sdout1, sdout3, sdout4 delay time from bclk1 ? ? to sync1 ? ? ( note 11 ) tbsyd 20 ns delay time from sync1 ? ? to bclk1 ? ? tsybd 100 ns serial data input latch setup time tb1ids 40 ns serial data input latch hold time tb1idh 40 ns delay time from sync1 to serial data output tsy1od 40 ns delay time from bclk1 ? ? to serial data output ( note 12 ) tb1od 40 ns sdin2, sdout2 sync2 duty cycle 50 % serial data input latch setup time tb2ids 40 ns serial data input latch hold time tb2idh 40 ns delay time from sync2 to serial data outputs tsy2od 40 ns delay time from bclk2 ? ?to serial data output ( note 13 ) tb2od 40 ns sdinn sdoutn (n=1, 2, 3) delay time from sdinn to sdoutn output tiod 60 ns note 11. when the polarity of bclk1 is inverted, delay time is from bclk1 ? ? note 12. when the polarity of bclk1 is inverted, delay time is from bclk1 ? ?. note 13. when the polarity of bclk2 is inverted, delay time is from bclk2 ? ?. switching characteristics
[ak7719] ms1351-e-00-pb 2012/01 9 timing diagram 1/fs 1/fs vih vil sync1/3 1/fbclk 1/fbclk vih vil bclk1/3 tbclk=1/fbclk ts=1/fs figure 2. system clock vil tpdn pdn figure 3. power-down
[ak7719] ms1351-e-00-pb 2012/01 10 tb1ids tbsyd tsybd vih sync1/3 bclk1/3 vil vih vil vih vil tb1idh sdin1/3/4 tsy1od sdout1/3/4 50%tvdd tb1od vih vil sdin2/4/3 tiod figure 4. serial data interface (port#1, 3, 4) tb2ids sync2 bclk2 vih vil tb2idh sdin2 tsy2od sdout2 50%tvdd tb2od 50%tvdd 50%tvdd vih vil sdin1 tiod figure 5. serial data interface (port#2)
[ak7719] ms1351-e-00-pb 2012/01 11 p interface (spi mode) (ta= -20oc ~ 85oc, vdd=1.2v; tvdd=1.6~3.6v, vss =0v; cl=20pf) note 14. except when input the eighth bit of the command code. tsclkh tsclkl 1/fsclk 1/fsclk trst1 tirrq sclk vih vil tsf tsr pdn csn vil vih vil vih figure 6. p interface 1 (spi) parameter symbol min typ max unit p interface timing (spi mode) sclk fall time tsf 30 ns sclk rise time tsr 30 ns sclk frequency fsclk 4.0 mhz sclk low level width tsclkl 120 ns sclk high level width tsclkh 120 ns csn high level width twrqh 500 ns from csn ? ? to pdn ? ? from pdn ? ? to csn ? ? trst1 tirrq 600 100 ns s from sclk ? ? to csn ? ? twsc 500 ns from sclk ? ? to csn ? ? tscw 800 ns si latch setup time tsis 100 ns si latch hold time tsih 100 ns ak7719 p delay time from sclk ? ?to so output tsos 100 ns hold time from sclk ? ? to so output ( note 14 ) tsoh 100 ns
[ak7719] ms1351-e-00-pb 2012/01 12 twrqh tsis tsih tscw tscw twsc csn si vih vil vih twsc sclk vil vih vil figure 7. p interface 2 (spi) tsos tsoh sclk vil vih so vih vil figure 8. p interface 3 (spi)
confidential [ak7719] ms1351-e-00-pb 2012/01 13 i2cbus interface (ta=-20oc~85oc, vdd=1.2v, vdd=1. 6~3.6v, vss =0v, cl=20pf) parameter symbol min typ max unit i2c timing scl clock frequency fscl 30 400 khz bus free time between transmissions tbuf 1.3 s start condition hold time (prior to first clock pulse) thd:sta 0.6 s clock low time tlow 1.3 s clock high time thigh 0.6 s setup time for repeated start condition tsu:sta 0.6 s sda hold time from scl falling thd:dat 0 0.9 s sda setup time from scl rising tsu: dat 0.1 s rise time of both sda and scl lines tr 0.3 s fall time of both sda and scl lines tf 0.3 s setup time for stop condition tsu:sto 0.6 s pulse width of spike noise suppressed by input filter tsp 0 50 ns capacitive load on bus cb 400 pf note 15. i 2 c-bus is a trademark of nxp b.v. thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 9. i 2 c bus interface
confidential [ak7719] ms1351-e-00-pb 2012/01 14 package 0.3850.029 0.1800.03 0.075 c c 0.5650.059 (0.040) 0.5 2.930.03 e dc a b 5 3 4 1 2 0.5 25 - 0.285 0.03 2.620.03 a top view 771 9 xxxx 1 25pin csp (unit: mm) a 0.05 m 0.15 m a c c b b material & lead finish package: epoxy, halogen (bromine and chlorine) free solder ball material: snagcu
confidential [ak7719] ms1351-e-00-pb 2012/01 15 marking a 1 7719 xxx x xxxx: date code (4 digit) date (yy/mm/dd) revision reason page contents 12/01/12 00 first edition revision history
confidential [ak7719] ms1351-e-00-pb 2012/01 16 important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. thank you for your access to akm product information. more detail product information is available, please contact our sales office or authorized distributors.

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